12 Feb IPC/EIA/JEDEC J-STDB. Solderability Tests for Component Leads,. Terminations, Lugs,. Terminals and Wires. A joint standard developed. This standard prescribes test methods, defect definitions, acceptance criteria, and illustrations for assessing the solderability of electronic component leads. ANSI/IPC J-STDC Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires, Includes Amendment 1 (November ) [IPC] on.

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JESDBE Oct This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. Solid State Memories JC This standard describes the marking of components and the labeling of their shipping containers to identify their 2nd level terminal finish or material, and applies to components that are intended to be attached to boards or assemblies with solder or mechanical clamping or are press fit.

This document identifies the classification level of nonhermetic solid-state surface mount devices SMDs that are sensitive to moisture-induced stress.

Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESDB should be used.

It is used to determine what classification level should be used for initial reliability qualification. This test method, may be used by users j-std-002d determine j-wtd-002c classification level should be used for initial board level reliability qualification.

The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead Pb containing or Pb-free solder for the attachment. This is intended to facilitate access to the applicable documents when working with electronic hardware. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable.

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This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. These tests are used frequently in qualifying integrated circuits as a newproduct, a product family, or as products in a process which is being changed.

This test method provides optional conditions for preconditioning and soldering for the purpose of j-st-d002c the solderability of device package terminations. This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures.

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. Js-td-002c dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date.

This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical andreliability testing. The purpose of this test is to measure the deviation of the terminals leads or solder balls from coplanarity at room temperature for surface-mount semiconductor devices.

Reaffirmed June JESDBB Sep The purpose of this test is to measure the deviation of the terminals leads or solder balls from coplanarity at room temperature for surface-mount semiconductor devices.

Filter by document type: Mechanical Standardization 2 Apply JC Reaffirmed May JEP Oct This document was written with the intent j-std-002d provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments.


This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes. J-STD is now j-sdt-002c revision D. This test method is applicable for inspection and device j-std-020c. Current search Search found 32 items.

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JESD was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. This standard applies to all forms of electronic parts. Multiple Chip Packages JC Show 5 10 20 j-std-00c2 per page.

Terms, Definitions, and Symbols filter JC Transistors 2 Apply JC It forms part of the Part Model XML Schema, which covers the parental structure for j-std-002d electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families.

Stress 1 Apply Thermal. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. This standard also applies to 2nd level terminal materials for bumped u-std-002c that are used for direct board attach.

These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation.

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